1. Field of the Invention
The present invention relates to communication networks and, more particularly, to a method and apparatus for designing a Phase-Locked Loop (PLL).
2. Description of the Related Art
Data communication networks may include various computers, servers, routers, switches, hubs, proxies, and other devices coupled to and configured to pass data to one another. These devices will be referred to herein as “network elements.” Data is communicated through the data communication network by passing data over an established circuit or by packetizing the data and routing the data packets between a series of network elements over the network.
There are two basic types of networks—Time Division Multiplexed (TDM) networks and packet networks. These two networks differ in how data are transmitted on the physical medium. In a TDM network, data belonging to different users are assigned different timeslots, otherwise called “circuits” or “channels” in a given time interval otherwise called a “frame”. A user can only transmit in its assigned time slot in a frame that continuously repeats itself. The clocking or timing signal that generates the frames and timeslots on the physical medium has to be very accurate for transmissions to be successful. Thus, in a TDM network, the network elements rely on accurate timing to determine which user data belong to which circuit, whereas in a packet network the packets are individually addressed in a manner that is able to be understood by the network elements. Since TDM networks rely on accurate timing to divide frames between multiple logical channels in existence on the same physical wire/optical fiber, timing requirements of TDM networks are generally relatively stringent. In a packet network, by contrast, timing is less important since each packet of data is self-contained and is able to specify to the network element its size and other associated parameters. Since timing is not as stringent on a packet network, the network elements on a packet network are generally not synchronized to a common timing source. Hence, packet networks are generally referred to as asynchronous networks.
TDM networks are synchronous in nature. Consequently, the equipment connected to a TDM network has to be synchronized to it in some manner. In a TDM network, a timing distribution network typically will link the TDM nodes to provide a synchronization signal that is traceable to a Primary Reference Source (PRS). The network synchronization signal is derived from the PRS and distributed through a hierarchy of network nodes with lesser stratum clocks. An alternative timing solution is to maintain a distributed PRS architecture, where for example, each TDM node is timed from an accurate timing source, such as a PRS/Stratum 1 clock, Global Positioning System (GPS) based clock, or a standalone accurate clock (e.g., H Maser, Cesium, Rubidium, etc.). The particular timing requirements on a service interface depend on the services (T1, E1, T3, E3, etc.) carried over the network, which are typically specified in a standard promulgated for that particular service type.
As packet technology has increased in reliability and sophistication, the cost of deploying packet-based networks such as Ethernet networks and Internet Protocol (IP) networks has dropped to the point where it is often cheaper to deploy a packet network than to deploy a TDM network. To take advantage of the lower costs of packet network technology, service providers have sought to implement packet-based core networks intermediate existing TDM networks. To allow a packet network to carry TDM traffic, the packet network must essentially behave as a transparent “link” in the end-to-end connection. The transparent inclusion of a packet network in an end-to-end path of a connection that carries circuit-switched time sensitive traffic is commonly referred to as “circuit emulation” on the packet network.
The non-synchronous nature of the packet network and the packetizing and depacketizing processes used to format the data for transmission over the packet network all contribute to increased delay and delay variations in the transmission of packets, which makes transfers of synchronization between the TDM networks on either side of the packet core difficult. Additionally, while packet networks are able to carry traffic between the end TDM networks, they do not naturally carry accurate clock information due to their asynchronous nature. Thus, to enable TDM traffic to be carried over a packet network, it is necessary to have the end systems directly exchange clock information, so that the data ports on the network elements can be synchronized and to allow the different networks to be synchronized.
To overcome the inherent non-synchronous nature of a packet network, a network element or a downstream terminal mode may use an adaptive timing technique to reconstruct the timing signal of the upstream TDM terminal. For example, where there are no reference clocks traceable to a PRS, a receiving TDM terminal node has to use an adaptive timing technique to reconstruct the timing signal of the transmitting TDM terminal. In an adaptive clocking technique, the TDM receiver derives an estimate of the transmitter clock from the received data stream. This is commonly done using a phase-locked loop (PLL) that slaves the receiver clock to a transmitter clock. The slave PLL is able to process transmitted clock samples encoded within the data stream, or process data arrival patterns, to generate timing signals for the receiver. The purpose of the slave PLL is to estimate and compensate for the frequency drift occurring between the oscillators of the transmitter clock and the receiver clock.
Several adaptive timing techniques have been developed, including extracting clock information from arrival patterns over the network, observing the rate at which the buffers are being filled, and using encoded timing signals transmitted from the upstream terminal to the downstream terminal across the packet network. One example of the use of encoded timing signals (timestamps) is described in U.S. patent application Ser. No. 10/076,415, entitled “Technique for Synchronizing Clocks in a Network”, the content of which is hereby incorporated by reference.
In this previous application, a PLL was developed that included a low-pass filter, however the PLL in that solution was not developed quantitatively, but rather was developed by experimental trials. To increase the performance of the PLL, such as to increase the jitter attenuation, a higher order PLL may be used at the slave clock. However, as the order of the PLL increases, such as where second and third order PLLs are to be used to increase the jitter attenuation performance of the PLL, designing a PLL by experimental trials becomes increasingly difficult and cumbersome. Accordingly, it would be advantageous to provide a software program configured to assist in the design of a PLL given a set of performance specifications, (e.g., system damping factor, etc.) and component characteristics (such as VCO characteristic curve, digital-to-analog (DAC) word size (in bits), etc.).